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Silicon Labs /EFR32MG21A020F768IM32 /PRS_S /ASYNC_SWLEVEL

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Interpret as ASYNC_SWLEVEL

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https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/PRS_S/ASYNC_SWLEVEL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0LEVEL)CH0LEVEL 0 (CH1LEVEL)CH1LEVEL 0 (CH2LEVEL)CH2LEVEL 0 (CH3LEVEL)CH3LEVEL 0 (CH4LEVEL)CH4LEVEL 0 (CH5LEVEL)CH5LEVEL 0 (CH6LEVEL)CH6LEVEL 0 (CH7LEVEL)CH7LEVEL 0 (CH8LEVEL)CH8LEVEL 0 (CH9LEVEL)CH9LEVEL 0 (CH10LEVEL)CH10LEVEL 0 (CH11LEVEL)CH11LEVEL

Description

No Description

Fields

CH0LEVEL

Channel Level
CH1LEVEL

Channel Level
CH2LEVEL

Channel Level
CH3LEVEL

Channel Level
CH4LEVEL

Channel Level
CH5LEVEL

Channel Level
CH6LEVEL

Channel Level
CH7LEVEL

Channel Level
CH8LEVEL

Channel Level
CH9LEVEL

Channel Level
CH10LEVEL

Channel Level
CH11LEVEL

Channel Level

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data